FLIR has not tested nor verified system level operation of the i.MX6 platform with the Muon’s parallel CMOS output. But the Muon’s parallel interface is a “Progressive” output, Refer to page 98 of the i.MX6 datasheet Rev 4 7/2015 regarding the “Gated Clock Mode”. The Muon’s Vsync stays high longer than shown, but the text states they look at the rising edge of VSYNC, so the fall being much later than shown should not be a problem. The i.MX6 can take YCvCr either in our 1X (x16 cmos) or 2X (x8 cmos) depending on how the device is configured. Interpreting the data as MSB/LSB for 14-bit raw should be a software choice. On page 100 of the i.MX6 datasheet the clock can be from 100kHz to 180MHz, and the Muon run between 10MHz and 40MHz which is well within the i.MX6’s capability.
Regarding the electrical levels, the Muon uses 3.3V LVCMOS. The i.MX6 “CSI” interface which involves these 20 pins is individually selectable, so the user should be able to put 3.3V on “NVCC_CSI”, which is pin N7 on the 21x21mm package (page 147). This pin applies to CSI0_DAT[19:4], CSI0_DATA_EN, CSI0_MCLK, CSIO_PIXCLK, AND CSI0_VSYNC (page 150), which should be all the pins needed to bring data in from the Muon’s parallel CMOS output.