Name

PyFive ASIC

Product Description

PyFive

The PyFive project was originally conceived as a libre silicon MCU capable of easily running Micropython/CircuitPython. It would host a VexRiscv processor and have a USB interface along with other standard peripheral interfaces. Stretch goals included having an FPGA interface and/or software defined peripherals.

In 2019, Google sponsored a free ASIC multi-project wafer (MPW) shuttle program in collaboration with eFabless and the SkyWater foundry. Not only did they provide an unprecedented open source PDK for the 130nm process node but also allowed teams to submit open source ASIC designs to a series of shuttles free of charge. The chip designs from up to 40 teams are added to an MPW and submitted for a fabrication shuttle on a regular cadence.

First Google-Sponsored MPW Shuttle Launched at SkyWater

The PyFive ASIC was one of the 40 designs selected to be included on MPW-1. The first PyFive design was intended to be a test of the ASIC implementation of the no2usb USB core by Sylvain Munat (tnt). The USB core was hardened along with some UART, video and PDM IP to fill in more of the available area on the chip design.

While waiting for the first batch of chips to be delivered, the PyFive team further developed the IP and a firmware implementation of CircuitPython on a special ECP5 FPGA board designed by Greg Davill.

Unfortunately, the MPW-1 had some hold time violations rendering the ASICs "dead on arrival" when delivered. The PyFive team in a ditch effort created a post mortem carrier design which allowed some signs of life to be extracted from the MPW-1 chips.

YouTube Video of tnt Bringing Pyfive MPW-1 Back to Life

The team has since found trouble finding the time to contribute due to the extremely busy schedules of the contributing team members. Though the PDK, tools, and shuttle are free, the engineering is not. As the major PyFive contributors are independent contractors, hours logged toward the project are cutting into their billable time.

This campaign aims to gather funding to pay the contributors to the PyFive project for their time. In turn the community is provided with new open hardware chip IP. To be clear, since this is a "GroupFund" and not a "GroupGet", no physical hardware shall be shipped to anyone.

Timeline

MPW-8

Since the initial MPW-1 chips had timing issues we weren’t able to verify the USB core.

For this MPW submission the plan is to re-harden the USB core and integrate it with a preliminary VexRiscv implementation. This will provide a base SoC that will be leveraged in subsequent designs. 

MPW-9

For the MPW-9 we plan to further implement various cores that will be bolted onto design from MPW-8. We won’t have the MPW-8 designs verified at the time of submission so plans for verification with the embedded Caravel management core will be considered.

ChipIgnite

For every $100K that is raised, $10K we will set aside in case we need to use chipIgnite shuttles if projects aren't selected for the free shuttle or want to accelerate development.

Core contributions

Funding will help support the development of the various IP components. 

IP Blocks

• USB
• UART
• PDM
• Simple video output
• Various RAM configurations (main RAM, caches, etc)
• PSRAM interface
• HyperRAM interface
• Flash interface
• ROM core generator
• Software defined peripheral block

The PyFive team will also continue to provide PCB design support, testing support and feedback for the Caravel project as a whole. 

Team

Check the team tab above for more information about our core developers.

Advisors

Sean Cross (xobs)

Scott Shawcraft (tannewt)

Matt Venn (mattvenn)

Tim Ansell (mithro)

Charles Papon (Dolu)

Product Specifications

Links

External Website