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CLEAR - The Open Source FPGA ASIC - by chipIgnite

CLEAR - The Open Source FPGA ASIC - by chipIgnite
Funded
0 of 1
CLEAR - The Open Source FPGA ASIC - by chipIgnite
107% Funded
200
Goal
215 of 200
Backed

$74.99 + Shipping
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Ending Date: Mon, 28 Mar 2022 18:10:00 PDT

Product Details

Name

CLEAR - The Open Source FPGA ASIC - by chipIgnite

Brand / Manufacturer

Efabless Corporation

Manufacturer Part #

CI00025

Product Description

CLEAR - The Open Source FPGA ASIC  

CLEAR is an Open Source FPGA ASIC delivered to you on its development board and its open source software development tools and all the ASIC design tools used to create it. That's for you to create your own - yes that's right - ASIC.

CLEAR is utilizing Caravel - the open source ASIC platform provided as a base System on Chip (SoC) provided by Efabless' chipIgnite offering.

What we will do

  1. Generate an embedded FPGA macro based on the famous OpenFPGA generator framework
  2. Integrate the eFPGA macro into Caravel which makes it an FPGA ASIC - Clear
  3. Manufacture the ASIC through chipIgnite program through SkyWater Technology
  4. Package and mount the ASIC on its development board 
  5. Test the boards before you get them along with the open source FPGA programing software
  6. You receive your board and have fun!

As part of the campaign we will show you everything we do including how to design your own ASIC with open source ASIC design software and how you can create a campaign just like this one for your own custom ASIC. All that without having to make a giant hole in your pocket for ASIC design and manufacturing. 

CLEAR - In the News

Features

  • 100% Open Source FPGA ASIC
  • A small but not-so-little 8x8 (64) CLB eFPGA
  • GitHub Repo: Efabless - CLEAR
  • CPU Subsystem
    • VexRISCV-based CPU
    • 3 kilobytes of on-chip RAM (2 kB of OpenRAM and 1 kB of DFFRAM
    • Executes directly from external QSPI flash
  • Peripherals
    • SPI master
    • UART
    • 39 software configurable GPIO 
    • Counter/Timers
    • Logic Analyzer
  • Additional features
    • Programmable internal clock frequency

CLEAR - Block Diagram

 

CLEAR - ASIC Pinout

 

Additional Cool Stuff

CLEAR - First Generation Development Board 

CLEAR - First Generation Wafers Before Packaging 

CLEAR - First Generation Board Blinky Test 

CLEAR - Low Power Consumption

It is an open source ASIC - That's why it is called CLEAR

Contact for bulk order inquiries over the 300 unit limit: contact@groupgets.com


Purchase Information

Unit Deliverable

One CLEAR OpenSource FPGA Development Board

Unit Price

$74.99

Availability

Not available / campaign Funded, end date: Mon, 28 Mar 2022 18:10:00 PDT

Lead Time

160 Days

Sponsors

Sponsor the great works of our community of developers and conservation technologists who are trying to make a real difference. Contact us at sponsor@groupgets.com for more information about becoming a campaign sponsor. For help or any other questions, please submit a support ticket here.

Help

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Approved

We are proud to support CLEAR - The Open Source FPGA ASIC - by chipIgnite in reaching its goal.

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