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CLEAR - The Open Source FPGA ASIC - by chipIgnite
CLEAR is an Open Source FPGA ASIC delivered to you on its development board and its open source software development tools and all the ASIC design tools used to create it. That's for you to create your own - yes that's right - ASIC.
As part of the campaign we will show you everything we do including how to design your own ASIC with open source ASIC design software and how you can create a campaign just like this one for your own custom ASIC. All that without having to make a giant hole in your pocket for ASIC design and manufacturing.
CLEAR - Block Diagram
CLEAR - ASIC Pinout
One CLEAR OpenSource FPGA Development Board
Not available / campaign Funded, end date: Mon, 28 Mar 2022 18:10:00 PDT
Campaign discussion forums are intended for questions about the product such as specifications or to share ideas about applications. The campaign initiator or GroupGets may also send out important one-to-many updates on this channel. This is not the place for individual technical support inquiries. For help or questions about an order, please submit a support ticket here.
I hope you are doing well and that you are making and hacking all around the world. This is the first update in a long time. After the campaign was funded the design team kicked the tires on design updates using updated version of the design flow OpenLane. CLEAR design was completed and conditionally submitted to manufacturing at SkyWater Technology Foundry for inspection and later processed to generate mask data. That means the design team continued to perform additional checks and verification steps in parallel with foundry inspection and data preparation effort.
During this process our team identified a critical issue related to on chip timing of the data and clock and started taking corrective actions that are still ongoing as we are factoring in learnings from available silicon from other parallel projects. As a result of the additional work it was no longer possible to push CLEAR to manufacturing in time for the April 2022 shuttle run.
We are aiming to send CLEAR to manufacturing - with all the updates and corrections - in the near future. Based on the cycle time and packaging lead time the earliest estimation of delivery is January 2023.
We really appreciate your patience and understanding. We will keep you posted with more frequent updates and answer your questions with full transparency. Your support makes such project possible. Thank you.
On behalf of the CLEAR Design Team
Sponsor the great works of our community of developers and conservation technologists who are trying to make a real difference. Contact us at email@example.com for more information about becoming a campaign sponsor. For help or any other questions, please submit a support ticket here.
We are proud to support CLEAR - The Open Source FPGA ASIC - by chipIgnite in reaching its goal.
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