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CLEAR is an Open Source FPGA ASIC delivered to you on its development board and its open source software development tools and all the ASIC design tools used to create it. That's for you to create your own - yes that's right - ASIC.
As part of the campaign we will show you everything we do including how to design your own ASIC with open source ASIC design software and how you can create a campaign just like this one for your own custom ASIC. All that without having to make a giant hole in your pocket for ASIC design and manufacturing.
CLEAR - Block Diagram
CLEAR - ASIC Pinout
One CLEAR OpenSource FPGA Development Board
Campaign Funded, scheduled end date: Thu, 04 May 2023 21:12:24 PDT
160 Days after campaign end date
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After a longer than expected journey, we are finally getting close to the finish line for fabrication of silicon for CLEAR. We are currently at 56% complete and now expecting wafers out of the foundry on October 5th. Once received, we have 2-3 weeks for QFN packaging followed by assembly on PCBA before shipping out.
You can track on progress of fabrication on the following link. The shuttle is 2304C.
Once we have silicon, we will be running running tests to validate functionality. We'll post results here as we complete that testing.
Thanks again for your continued support and patience on this project.
Following up on the last two updates. As you know CLEAR is built on the Caravel platform SoC. As mentioned before we have identified a timing issue from the earlier silicon. We have updated the open source design flow and redesigned CLEAR with the updated flow as well as checked the design integrity with proprietary solutions to ensure nothing slips.
While we were updating CLEAR embedded FPGA block, the Caravel chip with the fixes was being manufactured. We decided to hold sending off CLEAR to manufacturing until we test the fixes on physical silicon. That doesn't change the timeline my colleague Jeff DiCorpo mentioned below. CLEAR will be sent off to manufacturing in the next few days.
I am happy to report that in the last 48 hours we have received the Caravel chips (not including the eFPGA module) with the design corrections. We powered it up with our automated test setup and reported no IO timing issues! YES. This is the data we were waiting for before we push the button to send the full CLEAR SoC to manufacturing.
In the next couple of weeks we add more updates showing a new development board that we used which will be the same as the one you receive with your CLEAR board.
I would like to thank you again and must say again it takes a village and without your support we wouldn't be here.
We wanted to provide you an update for the project. As mentioned in the last post, we have been diligently working through making updates to the open source design flow and process to address the timing issues that were identified this last summer. The good news is that work is complete and we have released a new version of the Caravel chip that CLEAR uses as its base. This new version of Caravel has been used to reimplement chipIgnite designs which are now in fabrication.
That said, we still have concerns regarding the fabric implementation for the embedded FPGA in CLEAR. In addition to potential timing issues that exist inside this part of the design, the fabric for CLEAR was implemented using an architecture that is no longer consistent with the current version of the OpenFPGA program.
We are reviewing the FPGA implementation and will update the design it for a new submission of the project on April chipIgnite shuttle (2304C). The shuttle is currently projected to return Silicon in late July 2023.
We apologize for these delays and greatly appreciate your patience and continued support for this project. We will post another update for the project in late January as we complete the design review of the FPGA fabric.
I hope you are doing well and that you are making and hacking all around the world. This is the first update in a long time. After the campaign was funded the design team kicked the tires on design updates using updated version of the design flow OpenLane. CLEAR design was completed and conditionally submitted to manufacturing at SkyWater Technology Foundry for inspection and later processed to generate mask data. That means the design team continued to perform additional checks and verification steps in parallel with foundry inspection and data preparation effort.
During this process our team identified a critical issue related to on chip timing of the data and clock and started taking corrective actions that are still ongoing as we are factoring in learnings from available silicon from other parallel projects. As a result of the additional work it was no longer possible to push CLEAR to manufacturing in time for the April 2022 shuttle run.
We are aiming to send CLEAR to manufacturing - with all the updates and corrections - in the near future. Based on the cycle time and packaging lead time the earliest estimation of delivery is January 2023.
We really appreciate your patience and understanding. We will keep you posted with more frequent updates and answer your questions with full transparency. Your support makes such project possible. Thank you.
On behalf of the CLEAR Design Team
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We are proud to support CLEAR - The Open Source FPGA ASIC - by chipIgnite in reaching its goal.
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